FRAME/SLOT TIMING CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce a circuit scale in a frame/slot timing control circuit to be used for the synchronous processing of TDMA type data transmission.

SOLUTION: The frame/slot timing control circuit is provided with; a frame interruption counter 100 to be reset in each counting of frame length; an offset value register 101 for setting an offset value for controlling frame interruption timing; a comparator 102 for outputting a frame interruption signal when an output from the counter 100 is matched with an output from the register 101; a slot interruption counter 103 to be reset in each counting of slot length and reset to '0' by the frame interruption signal; and a comparator 104 for outputting a slot interruption signal when the count value of the counter 103 is '0'.

COPYRIGHT: (C)2004,JPO