发明名称 |
Semiconductor integrated circuit and its analyzing method |
摘要 |
A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.
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申请公布号 |
US2003200492(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20030452195 |
申请日期 |
2003.06.03 |
申请人 |
NAKAO MICHINOBU;YAMAGATA RYO;HATAYAMA KAZUMI;KOBAYASHI SEIJI;HIKONE KAZUNORI;SHIMAMURA KOTARO |
发明人 |
NAKAO MICHINOBU;YAMAGATA RYO;HATAYAMA KAZUMI;KOBAYASHI SEIJI;HIKONE KAZUNORI;SHIMAMURA KOTARO |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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