发明名称 |
On chip timing adjustment in multi-channel fast data transfer |
摘要 |
A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.
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申请公布号 |
US2003197534(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20020063394 |
申请日期 |
2002.04.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FENG KAI DI |
分类号 |
G06F11/00;H03L7/00;(IPC1-7):H03L7/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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