| 摘要 |
PURPOSE: An FIR(finite impulse response) filter is provided to realize FIR filters operation at a high frequency in a field programmable logic gate array board having a lower inner frequency. CONSTITUTION: A serial-to-parallel converter(10) divides an input signal into odd rows and even rows. A first FIR filter(FIR1) and a second FIR filter(FIR2) operate the odd rows and the even rows of the input signal at a relatively low frequency for bandpass-filtering the odd rows and the even rows respectively. A parallel-to-serial converter(20) alternately outputs the odd rows and the even rows filtered through the first and second FIR filters according to a selection signal, so that the parallel-to-serial converter outputs an output signal obtained by bandpass-filtering the input signal. |
