| 摘要 |
A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.
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