| 摘要 |
PURPOSE:To make the circuit execute equal high speed frequency dividing operation as a synchronous system irrespective of whether the value of (n) is large or small, by controlling the operation and reset of the TFF at the first stage of T (trigger type) FF's of (n) pieces by means of the DFF and a gate circuit operated by an input clock, circuit, in the asynchronous system frequency dividing circuit of (2<n>+1) frequency division. CONSTITUTION:The (2<n>+1) frequency dividing circuit is provided with the DFF10 operated by the input clock signals of the TFF's 6-8 of (n) pieces, the first gate circuit 9 for detecting that the 2<n> frequency division by the TFF's 6-8 of (n) pieces has been finished, and inputting its output to the data terminal of the DFF, and the second gate circuit 11 for obtaining the logical product of the output of the DFF10 and the output of the first gate circuit 9. And, by the second gate circuit 11, the TFF6 of the first stage among the TFF's 6-8 of (n) pieces is cleared (reset) immediately after the 2<n> frequency division is finished. |
