| 摘要 |
A line parameter detection circuit (70) of this invention includes an active video detector (72) that generates an "active video" signal (102) indicative of a video signal (100) containing video data that exceeds a predetermined threshold level. The line parameter detection circuit further includes three counters (82, 84, 86) that are incremented by a reference clock (110). The counters are reset and start counting reference clock pulses upon receiving an HSYNC pulse (104). A left edge register (90) stores the count accumulated in the first counter upon receiving a rising edge of the active video signal, a right edge register (92) stores the count accumulated in the second counter upon receiving a falling edge of the active video signal, and a line length register (96) stores the count accumulated in the third counter upon receiving the next subsequent HSYNC pulse. Each video signal scan line includes blanking periods (106, 108) between the HSYNC pulses and the active video region. The precise locations and timings of the blanking periods are typically unknown, however the period of the active video region is known because it coincides with the active video signal period. The timing ratio of the active video region to the blanking periods is determined from the line parameter detection circuit, from which the ratio of total blanking time to total line time is determined. The ratio of total blanking time to total line time is used to calculate the overall tracking period, and from that a tracking number n and pixel clock pulse frequency can be calculated.
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