IC LAYOUT SYSTEM EMPLOYING A HIERARCHICAL DATABASE

摘要

An IC layout system compiles a hierarchical netlist describing an IC into a database having a separate record for each cell and each module of the IC (Figure 1). Each database record references a cell library entry describing the cell or module and indicates a hierarchical relationship between its corresponding cell or module and other IC cells or modules. The system initially processes the database to reduce the number of cell and module records by combining hierarchically related cells and modules into larger cluster cells. The system then processes the database and cell library to generate a trial layout of the IC which positions highly interconnected cells near one another without regard to the hierarchical nature of the design. The system divides the IC design into separate partitions along hierarchical lines and then develops estimates of the size, shape and position of substrate area needed for each partition based on actual areas in the trial layout occupied by cells forming modules to be assigned to each partition (Figure 5). The system also allocates signal path timing constraints based on calculated path delays within the trial layout. The system thereafter processes the database and cell library to separately lay out each partition (Figure 12).