| 摘要 |
An output buffer circuit includes a delay circuit for delaying data signal or an inverted version of the data signal by a preset time, a buffer for buffering the data signal with an output impedance of a high value to output the resulting buffered signal, and a three-state buffer, which is controlled responsive to the output of the delay circuit and to the data signal, so that the three-state buffer is activated within the preset time to buffer the data signal and to output the buffered data signal, and is de-activated and turned off outside the preset time.
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