| 摘要 |
An apparatus and packaging method for stacking a plurality of integrated circuit substrates which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantable device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like. |
