发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To make an action highly speedy by installing a capacity cut MOSFET and using a control signal seperated from a load circuit of a word wire, etc. CONSTITUTION:When a stage circuit G composing an address decoder XDCR forms a high level non-selecting signal like power source voltage Vcc, an N channel MOSFETQ18 of a CMOS invertor circuit is on. At this time, when an output signal of the gate circuit G is set to a high level like power source voltage Vcc, a cut MOSFETQ16 is off. On the other hand, by a P channel MOSFETQ17 which is still on, gate voltage of a P channel MOSFETQ14 is set to a low level. Thus, since the P channel MOSFETQ14 is on and high voltage Vpp is applied to a gate of a P channel MOSFERQ15, the P channel MOSFETQ15, is set to off and a word wire W is set to a low level non-selecting condition.</p>
申请公布号 JPS6148196(A) 申请公布日期 1986.03.08
申请号 JP19840167823 申请日期 1984.08.13
申请人 HITACHI LTD 发明人 FUKUDA MINORU;FURUNO TAKESHI;MATSUNO YOICHI
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
代理机构 代理人
主权项
地址