发明名称 Method of predicting lifetime of semiconductor integrated circuit and method for reliability testing of the circuit
摘要 A time it takes for a total leakage current (i.e., a total amount of B-mode stress induced leakage currents) flowing through respective MOS devices in a semiconductor integrated circuit to reach a predetermined reference level is estimated as an expected lifetime of the circuit.</PTEXT>
申请公布号 US6633177(B1) 申请公布日期 2003.10.14
申请号 US20010744260 申请日期 2001.02.01
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD 发明人 OKADA KENJI
分类号 G01R31/28;H01L21/66;(IPC1-7):G01R31/02 主分类号 G01R31/28
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