发明名称 TEST SYSTEM FOR ADDRESS BUS
摘要 PURPOSE:To quickly test an address bus by setting a register on an address bus of a conventional circuit and executing an address bus test program with addition of a small number of circuits including a gate circuit, etc. CONSTITUTION:A register 4 has its output connected an input/output controller 3 and its input connected to an address bus line 10 respectively. An output line 22 is added to the controller 3 to transmit a turn-on signal when the 1st specific data is sent to the controller 3 and to turn off said turn-on signal when the 2nd specific data is sent to the controller 3. Then the gate circuits 23 and 25 latch the contents of the line 10 supplied to the register 4 by the memory read signal that is transmitted only when data are read out of a memory at output of a turn-on signal through the line 22. A CPU 1 latches the signals having all bits '0' and '1' sent to the line 10 via the register 4 and reads these signals out of the register 4 via the controller 3 to check the coincidence between this latched signal with the signal sent previously to the line 10.
申请公布号 JPH01232454(A) 申请公布日期 1989.09.18
申请号 JP19880058655 申请日期 1988.03.11
申请人 NEC ENG LTD 发明人 KOBAYASHI YOSHIAKI
分类号 G01R31/28;G06F11/22;G06F13/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利