发明名称 |
Selectable clocking architecture |
摘要 |
A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit and providing a second clock signal to a memory storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal.
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申请公布号 |
US2003190003(A1) |
申请公布日期 |
2003.10.09 |
申请号 |
US20020117702 |
申请日期 |
2002.04.05 |
申请人 |
FAGERHOJ THOMAS O. |
发明人 |
FAGERHOJ THOMAS O. |
分类号 |
G06F1/12;H03M9/00;H04L7/02;H04L25/05;(IPC1-7):H04L7/00;H04L25/00;H04L25/40 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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