发明名称 |
Method and apparatus for facilitating process-compliant layout optimization |
摘要 |
One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the specification that no not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
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申请公布号 |
US2003192013(A1) |
申请公布日期 |
2003.10.09 |
申请号 |
US20020116914 |
申请日期 |
2002.04.05 |
申请人 |
NUMERICAL TECHNOLOGIES, INC. |
发明人 |
COTE MICHEL LUC;HURAT PHILIPPE;PIERRAT CHRISTOPHE |
分类号 |
G03F1/14;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G03F1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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