Method and apparatus for implementing noise immunity and minimizing delay of CMOS logic circuits

摘要

A method and apparatus are provided for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits. A method of logical effort is applied to the CMOS logic circuits. Selected circuits within the CMOS logic circuits are checked for noise immunity utilizing a noise test simulation to identify each selected circuit failing the noise test simulation. An electrical effort is fixed to a value for providing noise immunity for each identified selected circuit failing the noise test simulation. The method of logical effort is applied to each remaining selected circuit not failing the noise test simulation. The sequential steps are repeated for each remaining selected circuit not failing the noise test simulation until no selected circuit failing the noise test simulation is identified. The selected circuits that are checked for noise immunity include, for example, dynamic circuits and passgate circuits. When none of the selected circuits fail the noise test simulation, or the electrical efforts have been fixed for all of the selected circuits failing the noise test simulation, the delay through the CMOS logic circuits has been minimized and the selected circuits are all assured of adequate noise immunity.