Port sampling circuit apparatus incorporated in a microcomputer

摘要

A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.