| 摘要 |
PROBLEM TO BE SOLVED: To limit the access from a CPU 1 as a device main control part to an I/O port by hardware without via device software. SOLUTION: The CPU 1 outputs as a writing command, writing data, address information, and a write signal which is a control signal. A bus buffer 2 is provided with a plurality of comparators 5 (5a, 5b,...5n) to configure the address to perform access limitation on an I/O device 4 and a signal converter 6 is provided at the output side of the comparators 5. The address, such as 1000, 2000,..., is configured on each comparator 5. The signal converter 6 disables the output of a write enable signal to an I/O port 3 after converting the write enable signal from the write enable signal to the write disable signal when the address configured on the comparator 5 and the address signal output from the CPU 1 match with each other. COPYRIGHT: (C)2004,JPO |
