发明名称 METHOD OF FORMING MULTILAYER METAL WIRING OF SEMICONDUCTOR ELEMENT
摘要 PROBLEM TO BE SOLVED: To provide a method of forming the multilayer metal wiring of a semiconductor element. SOLUTION: The method of forming the multilayer metal wiring of a semiconductor element comprises a process to form a first low dielectric constant insulation film on a semiconductor substrate where lower metal wiring is formed and then leave a predetermined thickness in this film on the lower metal wiring by etching the film for planarization, a process to form an etching barrier layer on the first low dielectric constant insulation film, a process to form a second low dielectric constant insulation film on the etching barrier layer, a process to form an oxide film on the second low dielectric constant insulation film, a process to etch, in a photoetching process, the oxide film, second low dielectric constant insulation film and etching barrier layer to form a via contact hole to expose the lower metal wiring, a process to form a bonding film/ diffusion preventing film on its entire surface including the via contact hole, and a process to form a contact plug for filling the via contact hole in order to form upper metal wiring connected to the contact plug. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003282709(A) 申请公布日期 2003.10.03
申请号 JP20020382343 申请日期 2002.12.27
申请人 HYNIX SEMICONDUCTOR INC 发明人 YOON JUN HO
分类号 H01L21/28;H01L21/3065;H01L21/3205;H01L21/768;H01L23/52;(IPC1-7):H01L21/768;H01L21/306;H01L21/320 主分类号 H01L21/28
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