发明名称 |
Compacted test plan generation for integrated circuit testing, test sequence generation, and test |
摘要 |
In a strongly testable DFT method, the length of a test sequence is reduced, thereby reducing the amount of circuitry to be added for testing purposes. Test plans, generated one for each of circuit elements forming a data path, are scheduled in parallel in a form that can be compacted, and a compaction operation is applied to generate a compacted test plan. The test sequence is generated by inserting the test patterns needed for each circuit element into the compacted test plan.
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申请公布号 |
US2003188239(A1) |
申请公布日期 |
2003.10.02 |
申请号 |
US20020208110 |
申请日期 |
2002.07.29 |
申请人 |
HOSOKAWA TOSHINORI;DATE HIROSHI;MURAOKA MICHIAKI |
发明人 |
HOSOKAWA TOSHINORI;DATE HIROSHI;MURAOKA MICHIAKI |
分类号 |
G01R31/3183;G01R31/28;G01R31/317;G06F11/22;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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