发明名称 Method and apparatus for delay fault testing
摘要 A TAP-controlled scan architecture is modified to include an additional pin to receive a double capture mode (DCM) signal that may be used to override a functional mode signal provided by a TAP controller to enable an externally generated functional clock to provide double capture clock pulses to an internal scan chain during testing without transitioning the TAP controller between states.
申请公布号 US2003188243(A1) 申请公布日期 2003.10.02
申请号 US20020113365 申请日期 2002.03.29
申请人 RAJAN KRISHNA B. 发明人 RAJAN KRISHNA B.
分类号 G01R31/3185;(IPC1-7):G01R31/28 主分类号 G01R31/3185
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