| 摘要 |
A method of manufacturing an array substrate having drive integrated circuits and first and second semiconductor layers made of single crystalline silicon. First and second gate electrodes are formed over the first and second semiconductor layers, wherein the first and second gate electrodes are narrower than the first photoresist patterns. First and second insulator patterns are formed on the first and second semiconductor layers, wherein the first and second insulator patterns having a substantially equal width to the first photoresist patterns. N<+ >ion doping is carried out using the first photoresist pattern as a mask. The first photoresist patterns are ashed, thereby the first photoresist patterns become reduced first photoresist patterns, wherein the reduced first photoresist patterns have substantially the same width as the first and second gate electrodes. A second photoresist pattern is formed, which covers the first gate electrode and the first semiconductor layer. P<+ >ion doping is carried out using the second photoresist pattern as a mask. The p<+ >ion dose is larger than the n<+ >ion dose.
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