| 摘要 |
PROBLEM TO BE SOLVED: To easily meet the minimum condition of setup time of a flip-flop without any influence upon normal operation even if the clock delay from a clock input terminal of PCI master device to a clock input end of the flip-flop is decreased to shorten the output data determination time. SOLUTION: This PCI master device is provided with an abort circuit 20 for aborting transaction when assertion of a device selection signal is not detected in each rise of a clock signal within four clock cycles from the address phase end. In aborting, a D flip-flop 23 is interposed in a data signal line of the abort circuit 20 so that the transaction end and start timing is delayed by one clock. Since interposition does not exert any influence on the normal operation, the transaction end processing in the normal operation is started without one clock cycle delay. COPYRIGHT: (C)2003,JPO
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