| 摘要 |
A multi-processing computer architecture (100) and a method of operating the same are provided. The multi-processing architecture (100) provides a main processor (102) and multiple sub-processors (104, 106, 108, 110) cascaded together to efficiently execute loop operations. The main processor (102) executes operations outside of a loop and controls the loop. The multiple sub-processors (104, 106, 108, 110) are operably interconnected, and are each assigned by the main processor (102) to a given loop iteration. Each sub-processor (104, 106, 108, 110) is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor (106, 108, 110).
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