| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a systematically well-matched clock device in a computer system, not generating inverted phenomenon or jump of a time. <P>SOLUTION: A first clock 12a counts the output of a first frequency dividing circuit 14a wherein an originated frequency of a clock of an oscillator 13 is divided by a prescribed frequency dividing ratio, and ticks for external processing. A second clock 12b counts the output of a second frequency dividing circuit 14b wherein the originated frequency of the clock of the oscillator 13 is divided by a prescribed frequency dividing ratio, and ticks for internal processing. A time correction processing part 15 corrects times of the first clock 12a and the second clock 12b to the reference time of a reference clock 17. Thereby, time correction of the first clock 12a is performed so as to be fit for the external processing, and time correction of the second clock 12b is performed so as to be fit for the internal processing. <P>COPYRIGHT: (C)2003,JPO</p> |
