Apparatus and method for resolving an instruction conflict in a software pipeline nested loop procedure in a digital signal processor

摘要

A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. A second software procedure can be initiated prior to the completion of first software procedure. The apparatus can execute an inner nested loop of a nested loop instruction set as a software pipeline procedure. The inner nested loop instruction set is stored in a buffer memory unit during the execution of the outer nested loop instruction set. The epilog of the inner nested loop instruction set can overlap the execution of the outer loop instruction set and the execution of the prolog of the next inner nested loop procedure. Apparatus is provided for resolution of instruction conflict in overlapping inner loop and outer loop instruction execution.