发明名称 ZEITVERTEILTE ENTFERNUNG VON FEHLERKORREKTURCODES (ECC) ZUR KORREKTUR VON SPEICHERFEHLERN
摘要 Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section-the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.
申请公布号 DE69719086(T2) 申请公布日期 2003.09.25
申请号 DE1997619086T 申请日期 1997.11.24
申请人 INTEL CORPORATION, SANTA CLARA 发明人 HAYEK, R.;VENKATARAMAN, RADHAKRISHNAN;AJANOVIC, JASMIN
分类号 G06F11/10;(IPC1-7):G06F11/08;G11C29/00 主分类号 G06F11/10
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