| 摘要 |
An electronic circuit comprising a frequency or phase-locked loop (PLL) comprising a first input terminal (1) coupled to receive a first input signal (D); a second input terminal (2) coupled to receive a second input signal (CLK); detection means (DMNS) for comparing the frequency or phase of the first input signal (D) with the frequency or phase of the second input signal (CLK), respectively, and for supplying directly or via a charge pump (CHPPMP) a control voltage (Vcntrl) as a result of the comparison of the first (D) and second (CLK) input signals; a control transistor (T0) having a first main terminal and a control terminal which are coupled to receive the control voltage (Vcntrl) and having a second main terminal for supplying a control current (Icntrl) responsive to the control voltage (Vcntrl); a capacitor (C) coupled in between the first main terminal and the control terminal; a current controlled oscillator (CCO) having an input terminal (CCOI) coupled to receive the control current (Icntrl) and having an output terminal (CCOO) for supplying directly or via frequency dividers the second input signal (CLK) having a frequency or phase which is synchronized with the frequency or phase, respectively, of the first input signal (D); and a stabilizing circuit (STB) for stabilizing the frequency or phase-locked loop (PLL) by adding a zero to the loop transfer function of the frequency or phase-locked loop (PLL). The stabilizing circuit (STB) further comprises a further charge pump (CHPPMPF) for delivering a compensation current (Iz) to the input terminal (CCOI) of the current controlled oscillator (CCO), while the compensation current (Iz) may have an approximately zero value, a negative value, or a possitive value dependent on control signals (FUP, FDN) delivered by the detection means (DMNS), and the absolute value of said positive or negative value roughly linearly depends on the control voltage (Vcntrl). |
