Clocking scheme and clock device for a monolithic integrated circuit

摘要

The schema includes a base clock generated by a clock source (1) coupled to intermediate clocks (c1,..) delayed with respect to each other by delays distributed within a period of the base clock. Each intermediate clock supplies at least one data processing block (D1-DM) in the integrated circuit. The delay for a transmitting block is longer than that for a receiving block to which it is transmitting. AN Independent claim is also included for the following: a timing device for a monolithic integrated circuit.