| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To accurately synchronize internal clocking with external clocking in a system for performing data transfer synchronously with the internal clocking. <P>SOLUTION: The external clocking CK becomes the internal clocking CLK having a skew D1 via a buffer 13. The internal clocking CLK becomes a corrected internal clocking CK' via a delay circuit 32 having the delay quantity A, a delay unit array 33-1 to 33-n forming the delay quantity 2×Δand a delay circuit 34 having the delay quantity D2, to be synchronized with the external clocking CK. Each delay unit has a state holding part, and the state holding part is fixed in the prescribed state in the delay unit where a forward pulse passes. Hereby, the delay quantity 2×Δis formed accurately. <P>COPYRIGHT: (C)2003,JPO</p> |
