发明名称 MEMORY DATA SHARING SYSTEM BY A PLURALITY OF STATIONS HAVING A PLURALITY OF COMMUNICATION LINES
摘要 <P>PROBLEM TO BE SOLVED: To provide a memory data sharing system in which stations can transmit and receive data to/from each other and which can continuously function even when a certain station fails to function or even when a failure occurs in a communication line. <P>SOLUTION: In this system, a specific station address value is set to each of stations, and each time is made to correspond to the address value of each station. All internal clocks (39) in the stations show the same time and circulates from a time Too to an upper limit time TM. When the internal clocks (39) show a time corresponding to the station address value of a certain station, data in memories (38) located at a memory address corresponding to the station address value is embedded in a packet (9) and transmitted to communication lines (33A and 33B). An allowable time error determination circuit (34) compares a calculated correct time of the internal clock of its own station with a time indicated by the internal clocks (39), and corrects the internal clocks (39) if the time indicated by the internal clocks (39) exceeds an allowable time error range. The system is provided with a plurality of the communication lines (33A and 33B), if a change in a bit showing a connection state to respective stations occurs, other communication lines (33B) is utilized. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003264561(A) 申请公布日期 2003.09.19
申请号 JP20020066271 申请日期 2002.03.12
申请人 STEP TECHNICA CO LTD 发明人 MUGITANI YOSHIHIRO
分类号 B60R21/16;B60R21/01;G06F11/20;G06F15/167;G06F15/177;H04L7/00;H04L12/28;H04L12/707;H04L12/709 主分类号 B60R21/16
代理机构 代理人
主权项
地址