SEMICONDUCTOR MEMORY IMPROVED FOR TESTING

摘要

A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, various combinations of the capacitors are connected to the signal wire and the signal timing is then measured. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.