发明名称 Interconnect-aware methodology for integrated circuit design
摘要 An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.
申请公布号 US2003172358(A1) 申请公布日期 2003.09.11
申请号 US20020091934 申请日期 2002.03.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALON AMIR;GOREN DAVID;GORDIN RACHEL;LIVSHITZ BETTY;SHERMAN ANATOLY;ZELIKSON MICHAEL
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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