发明名称 VERFAHREN ZUR HERSTELLUNG EINES SILIZIUM/INTEGRIERTE SCHALTUNG WAFERS
摘要 A method for making integrated circuit wafers wherein the wafer has vias or other openings in the wafer which openings have a barrier/adhesion or other metal layer which is metallized to form the circuit comprising activating the metal layer and then sensitizing the metallic layer using a sensitizing displacement composition comprising preferably an alkaline palladium non-ammonia nitrogen (ethylene diamine) complex which is contacted with the wafer at a specially controlled pH. The wafer is activated using an activation solution which contains a complexing agent for any dissolved metal. The sensitizing solution also preferably contains a complexing agent for dissolved metal and preferably contains a second complexing agent such as EDTA to solubilize base metal contaminants.
申请公布号 DE69624130(T2) 申请公布日期 2003.09.11
申请号 DE1996624130T 申请日期 1996.12.11
申请人 ENTHONE-OMI, INC. 发明人 OBERLE, R.
分类号 C23C18/26;C23C18/18;H01L21/288;H01L21/308;H01L21/768;(IPC1-7):B05D5/12;B05D1/18;B05D3/04;C23C18/16;C23C18/28 主分类号 C23C18/26
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