发明名称 MEMORY MODULE ASSEMBLY USING PARTIALLY DEFECTIVE CHIPS
摘要 A method of fabricating a memory module according to one embodiment, a clock booster is mounted on a multi-layer circuit bard (101). The clock booster may be any apparatus that receives a clock input, and output one or more clock signals capable of driving a multiplicity of logic parts without clock distortion. In a preferred embodiment, a phase-locked loop circuit may be used as a clock booster. The test and patching (102) allows a fully-functional memory part adds, it is desirable to only connect the clock signal to those memory parts that are utilized. This may be accomplished using any number of switching mechanisms to connect or disconnect a clock signal to a memory part. In a preferred embodiment, a clock patching network may be used to selectively connect or disconnect outputs of a clock booster to the memory parts (103).
申请公布号 WO03073356(A1) 申请公布日期 2003.09.04
申请号 WO2003US05845 申请日期 2003.02.24
申请人 CELETRON INTERNATIONAL, LTD.;CELETRON USA 发明人 PEDDLE, CHARLES, I.
分类号 G11C5/06;G11C29/00;H01L21/66;H01L23/00;H05K1/00;H05K1/18;H05K3/22 主分类号 G11C5/06
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