| 摘要 |
PURPOSE: A fabrication method of an integrated circuit is provided to efficiently reduce a chip size by using a defined epitaxial layer of an HBT(Heterojunction Bipolar Transistor) as a resistor having a large resistance and using another defined epitaxial layer as a stabilizing resistor. CONSTITUTION: After removing an emitter cap layer(9), an emitter layer, and a surface of a base layer, base metal electrodes(11) is formed on both sides of an emitter metal electrode(10). After etching the base layer, a collector layer, and a surface of a second selective etch layer, the second selective etch layer is selectively etched compared to a subcollector layer. The entire subcollector layer is removed except for an active device part included region and a lowly resistive resistor(14) region. Collector metal electrodes(12) are formed on the active device part included region, the lowly resistive resistor(14), and defined regions of a second selective etch layer(3) having a high resistance. Then, the second selective etch layer(3) is selectively removed and a partial etching step is performed for isolation between the active and passive devices.
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