发明名称 Clock receiver circuit for on-die salphasic clocking
摘要 A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
申请公布号 US6614279(B2) 申请公布日期 2003.09.02
申请号 US20010941457 申请日期 2001.08.29
申请人 INTEL CORPORATION 发明人 ANDERS MARK A.;KRISHNAMURTHY RAM K.;SOUMYANATH KRISHNAMURTHY
分类号 G06F1/10;(IPC1-7):H03F3/45 主分类号 G06F1/10
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