Low voltage, high speed CMOS CML latch and MUX devices

摘要

A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.