发明名称 |
Selection based rounding system and method for floating point operations |
摘要 |
A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.
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申请公布号 |
US6615228(B1) |
申请公布日期 |
2003.09.02 |
申请号 |
US20000583362 |
申请日期 |
2000.05.30 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, LP |
发明人 |
COLON-BONET GLENN T;BASS STEPHEN L |
分类号 |
G06F7/38;G06F7/483;G06F7/544;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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地址 |
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