| 摘要 |
PROBLEM TO BE SOLVED: To perform optimum formations of an n-MOS and p-MOS of a CMOS. SOLUTION: A manufacturing method of the CMOS includes a step (S5) for forming second spacers on sidewalls of gates of the n-MOS and p-MOS after forming their sources and drains by first activating annealing, a step (S6) for implanting impurities into source/drain extensions of the n-MOS, a step (S7) for performing thereafter second activating annealing, a step (S8) for implanting impurities into the source/drain extensions of the p-MOS, and a step (S9) for performing thereafter third activating annealing. Consequently, the n-MOS is formed by the second and third activating annealing, and the p-MOS is formed by the third activating annealing. That is, an enough thermal budget can be given to the n-MOS and the necessary thermal budget of the p-MOS can be suppressed at a minimum, to make possible the optimum formations of the source/drain extensions of the CMOS. COPYRIGHT: (C)2003,JPO
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