| 摘要 |
PROBLEM TO BE SOLVED: To provide a dual port RAM access control circuit which transfers data at a high speed without any competition to the signal transferred from two processors when accessing a dual port RAM. SOLUTION: An RE and WE generation circuit 30 generates an enable signal of the cycle shorter than the cycle of read-enable and write-enable of two processors, and generates the control signal to give access priority to a dual port RAM to the processor which is firstly accessed to an arbitration circuit 40 based on the signal. A delay control circuit 50 transfers the signal to the dual port RAM without any delay regarding the processor firstly accessed based on the control signal, and transfers the signal to the dual port RAM through the delay regarding the secondly accessed processor. For the data control between each processor and the dual port RAM, the signal to access the dual port RAM by a latch circuit 60 is used for the control signal for temporarily saving or transferring data. COPYRIGHT: (C)2003,JPO
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