METHOD OF FORMING A FULLY-DEPLETED SOI (SILICON-ON-INSULATOR) MOSFET HAVING A THINNED CHANNEL REGION

摘要

A sub-0.05 mum channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 mum channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.