| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit for normally precisely detecting a center level and correcting it even when an FSK signal is received with the superimposition of the frequency change of a transceiver when the length of a code, i.e., '1' or '0' is drastically long in the FSK signal. SOLUTION: The hold circuits HLD1 and HLD2 of sample values which are respectively exclusive for the '1' and '0' of an input demodulation data signal are arranged. A differential voltage between the both sample values is temporarily converted into a digital code and, then, re-converted into an analog value, so that holding is digitally performed. When '1' continues, a hold voltage with respect to '1' is gradually updated to a new value and, at the same time, a voltage obtained by subtracting the differential voltage from the hold voltage is added to the hold circuit for '0', and updated to the new value. When the '0' continues, on the contrary, the hold circuit for '1' is updated through the use of a voltage which is obtained by adding the differential voltage to the hold voltage together with self-updating. Thus, data information is determined as the reference value of a comparator CMP with the average value of the both hold voltages as a center level value. COPYRIGHT: (C)2003,JPO
|
