Memory devices having power supply routing for delay locked loops that counteracts power noise effects

摘要

A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.