| 摘要 |
<p>A memory region is provided with a memory cell transistor and a planar-type capacitor, and a logic circuit region with CMOS transistors. A capacitor insulating film (15) of the planar-type capacitor and a plate electrode (16b) are provided over a trench shared with a shallow trench isolation (12a), so that the upper part of the trench is filled with the capacitor insulating film (15) and the plate electrode (16b). An end part of an n-type diffused layer (19) that is a storage node is formed along the side face of the upper part of the trench to a region overlapping with the shallow trench isolation (12a). The area of a part functioning as a capacitor is increased without increasing the substrate area.</p> |
