| 摘要 |
This invention provides an apparatus and a method for automatically verifying a designed semiconductor integrated circuit (LSI). The apparatus verifies a circuit generated by a generator for generating a circuit diagram of the whole LSI in accordance with the arrangement of basic cells which define a predetermined circuit unit. At least one of basic cells includes a verification symbol specifying a name and verification contents of a node to be verified. The apparatus analyzes a circuit diagram of the whole LSI generated in accordance with the arrangement having a cell including verification symbols to extract names and verification contents of the nodes to be verified, generates a verification pattern in accordance with the extracted node name and verification contents, executes a circuit simulation by using the verification pattern, analyzes the simulation result, and determines whether a the verified node is accepted or rejected.
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