发明名称 |
Automatic delay technique for early read and write operations in synchronous dynamic random access memories |
摘要 |
An automatic delay technique for early "read" and "write" memory access operations in synchronous dynamic random access memory ("SDRAM") devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select ("Yi") and data signals such that the column address strobe ("/CAS") signal is allowed to go "active" in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals ("read" or "write") are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.
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申请公布号 |
US6608797(B1) |
申请公布日期 |
2003.08.19 |
申请号 |
US20020125756 |
申请日期 |
2002.04.18 |
申请人 |
UNITED MEMORIES, INC.;SONY CORPORATION |
发明人 |
PARRIS MICHAEL C.;HARDEE KIM C.;JONES, JR. OSCAR FREDERICK |
分类号 |
G11C11/407;G11C7/10;G11C11/408;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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