发明名称 COUNTER CIRCUIT AND PLL CIRCUIT USING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem of a large through-current flowing due to a maximum transition of data, while a ripple counter counts up/down, this causing a noise having adverse influences on neighboring analog circuits. <P>SOLUTION: The counter circuit comprises: a flip-flop circuit 12 composed of three parallel arranged D-FFs 121, 122, 123 with program value loading functions for applying gray codes of 3 bits (b2, b1, b0) converted and given by a code converter circuit 11 for every bit to inputs P of the D-FFs; a logic circuit 13 for executing logical operations on a truth table, for realizing gray counters for outputs of the D-FFs 121, 122, 123 to give the operation result to inputs D of these D-FFs; and an output circuit 14 for taking the logical product of each of the outputs of the D-FFs 121, 122, 123 as a count output, thus suppressing the through-current and the delay in transition of data. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003229761(A) 申请公布日期 2003.08.15
申请号 JP20020026250 申请日期 2002.02.04
申请人 SONY CORP 发明人 HARADA SHINGO
分类号 H03K23/48;H03K23/00;H03L7/08;H03L7/183 主分类号 H03K23/48
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