发明名称 WIRING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To efficiently arrange wirings. SOLUTION: A plurality of circuit blocks is arranged at first, and a plurality of virtual wirings is arranged temporarily in a clearance between the plurality of virtual wirings. Then, a plurality of leading-out wires is led out from the plurality of circuit blocks, based on connection information, so as to be connected to the virtual wirings arranged temporarily. Conditions of the leading-out and the plurality of virtual wirings are verified thereafter. Arranging positions of the plurality of virtual wirings are changed in response to a verified result therein to prepare a wiring pattern. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003228596(A) 申请公布日期 2003.08.15
申请号 JP20020028311 申请日期 2002.02.05
申请人 SANYO ELECTRIC CO LTD 发明人 KANO KAZUYUKI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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