| 摘要 |
<p>A method of designing an integrated circuit for distributing test clock signals to embedded cores (FIG. 2) having at least one core functional clock input comprises, for each core, providing a clock gating circuit (46) for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit (50) for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.</p> |
